This application claims benefit of priority under 35USC xc2xa7119 to Japanese patent application No. 2000-089372, filed on Mar. 28, 2000, the contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to a semiconductor inspecting system, a semiconductor defect analyzing system, a semiconductor design data modifying system, a semiconductor inspecting method, a semiconductor defect analyzing method, a semiconductor design data modifying system, and a computer readable recorded medium. More specifically, the invention relates to the quantitative analysis of defects, which are generated in a semiconductor device in accordance with the characteristics of the design of the device, the analysis of the cause of the defects, which is carried out on the basis of the quantitative analysis, and the modification of the design using these analyses.
2. Description of the Prior Art
In a conventional inspection in semiconductor devices, particularly in an inspection in an irregular or random pattern, there is used a method for comparing the pattern of a chip C2, which is an object to be inspected, with the pattern of another chip Cl among chips in a semiconductor substrate S to detect the difference there between as a defect DF, as shown in, e.g., the schematic diagram of FIG. 1. According to this detection method, it is required to carry out the inspection for a long time when the area of an inspection region is extended in accordance with the extension of the area of the chip or when the detection sensitivity is raised in order to detect finer defects. In order to shorten the inspection time, there is carried out a so-called random sampling for choosing a region, which is to be inspected in a chip, and a chip, which is to be inspected, at random.
However, when the random sampling is carried out, the true number of defects can not be grasped if the positions of defects are biased, so that there is a problem in that erroneous results are obtained when the total number of defects is quantified.
There are also relatively similar patterns among random patterns. If the random sampling is carried out with respect to such patterns, similar patterns are duplicated to be chosen. For that reason, when defects caused by the characteristics of the patterns are intended to be detected, the inspection efficiency is not only bad, but a pattern to be inspected is also not chosen as an object to be inspected, so that some defects are overlooked.
On the other hand, conventionally, when the cause of defects is intended to be analyzed, detected defects are observed by an electron microscope or the like, and the cause of the defects is guessed. However, it can not be clarified how such defects are caused, particularly, what characteristics of patterns or processes, what variation and what probability the defects are generated, or how these causes are combined to generate the defects, and what range of design characteristics and variation in processes cause the defects.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor inspecting system, semiconductor inspecting method and computer readable recorded medium for precisely and efficiently qualifying and outputting defects which are generated in a pattern in accordance with the characteristics of a design.
It is another object of the present invention to provide a semiconductor defect analyzing system, semiconductor defect analyzing method and computer readable recorded medium for analyzing the cause of defects, which are generated in a pattern, in connection with information on a design characteristic and a process result.
It is a further object of the present invention to provide a semiconductor data modifying system, semiconductor data modifying method and computer readable recorded medium capable of utilizing the result of the analysis of defects to modify the design of a pattern in a design stage before a semiconductor process so that the possibility of generating defects is lower.
According to a first aspect of the present invention, there is provided a semiconductor inspecting system comprising: a first memory for storing therein a design data of a semiconductor device; a data retrieving part for extracting an inspected-object region from the first memory, the inspected object region being a region serving as an object to be inspected; a design characteristic item data preparing part for deriving numerical values indicative of design characteristics of the design data every one of lattice regions which are obtained by dividing the inspected object region extracted by the data retrieving part into lattices of an optional size and for preparing a design characteristic item data; a characteristic classification preparing part for classifying the design characteristic item data into a desired number of groups to prepare a characteristic classification data; a sampling part extracting the lattice regions at random from the characteristic classification data at a certain sampling rate with respect to the number of the lattice regions belonging to the groups; a second memory for storing therein a defect inspection data which is a data concerning a defect obtained by inspection with respect to a pattern of the lattice regions extracted at the sampling rate from processed patterns which are processed on the basis of the design data; and an operation part for calculating the number of defects in the whole inspected object region on the basis of the defect inspection data, the character classification data and the sampling rate.
According to the first aspect of the semiconductor inspecting system according to the present invention, the design characteristic item data preparing part derives a numerical number indicative of the design characteristic of the design data and prepares the design characteristic item data, and the characteristic classification data preparing part classifies the design characteristic item data into the desired number of groups to prepare the characteristic classification data. Moreover, the operation part calculates the number of defects in the whole inspected object region on the basis of the defect inspection data, the character classification data and the sampling rate. Therefore, it is possible to more accurately quantify defects caused by a design of a semiconductor device.
It is advantageous in the semiconductor inspecting system that the defect inspection data include a data on the degree of defects and the operation part outputs the sum total of defects every degree of defects.
The defect inspection data may be a data obtained by comparing an ideal shape data, which is a simulation result based on the design data, with a shape data of the defects in the processed pattern.
The characteristic classification data preparing part may classify the design characteristic item data using a neural network.
According to a second aspect of the invention, there is provided a semiconductor defect analyzing system comprising: a first memory for storing therein a design data of a semiconductor device; a data retrieving part for extracting an inspected object region from the first memory, the inspected object region being a region serving as an object to be inspected; a second memory for storing therein a defect inspection data concerning an actual defect and a degree of the defect which are obtained by inspecting a processed pattern which is processed on the basis of the design data; a design data processing part for acquiring a first lattice region by dividing the inspected object region by a lattice having an optional size on the defect inspection data so that a place at which the defect has occurred is arranged at the center thereof, the optional size being given as a parameter, and for acquiring a second lattice region by dividing the inspected object region by the lattice on the basis of the defect inspection data so that a non-defective place of the processed pattern is arranged at the center thereof, the non-defective place being a place which is appropriately processed, and for preparing a first design characteristic item data and a second design characteristic item data every second lattice region and every second lattice region respectively by deriving a numerical value indicative of a design characteristic of the design data every first lattice region and every second lattice region respectively; a third memory for storing therein a data on an observable process result relating to a processing of the pattern based on the design data; a process data processing part for collecting a value of a first process result corresponding to a pattern in the first lattice region, and a value of a second process result corresponding to a pattern in the second lattice region; and a defect occurrence rule preparing part for preparing a defect occurrence rule by correlating a combination of the first design characteristic item data and a value of the first process result with the defect and the degree of the defect and by correlating a combination of the second design characteristic item data and a value of the second process result with the defect and the degree of the defect.
According to the second aspect of the semiconductor defect analyzing system according to the present invention, the defect occurrence rule preparing part prepares the defect occurrence rule by correlating the combination of the first design characteristic item data and the first process result value with the defect and the degree of the defect and by correlating the combination of the second design characteristic item data and the second process result value with the defect and the degree of the defect, so that it is possible to calculate the defect occurring probability with respect to the combination of the design characteristic and the process result causing the defect, the presence of a defect and the degree thereof. Consequently, it is possible to calculate a defect occurring probability with respect to the combination of a design characteristic causing the defect, the process result, the presence of the defect and the degree thereof.
The defect inspection data may preferably be a data prepared on the comparison of an ideal shape data with a shape data of the defect in the processed pattern, the ideal shape data being a simulation result based on the design data.
In the semiconductor defect analyzing system according to the second aspect, it is advantageous that the plurality of lattice sizes are given as the parameters, the design data processing part changes the lattice sizes on the basis of the parameters to prepare the first design characteristic item data and the second design characteristic item data with respect to the plurality of first lattice regions and the plurality of second lattice regions, respectively, the process data processing part collecting a value of the first process result and a value of the second process result from the third memory with respect to the first lattice regions having a plurality of sizes and the second lattice regions, respectively, the defect occurrence rule preparing part preparing the defect occurrence rule by correlating a combination of the lattice size, the first design characteristic item data and a value of the first process result with the defect and the degree of the defect and by correlating a combination of the lattice size, the second design characteristic item data and a value of the second process result with the defect and the degree of the defect.
According to a third aspect of the present invention, there is provided a semiconductor defect analyzing system comprising: a first memory for storing therein a design data of a semiconductor device; a second memory for storing therein a first size and a second size as parameters, the first size and the second size being optional sizes of a lattice used for dividing an inspected object region of a semiconductor device, and, the inspected object region being a region serving as an object to be inspected; a data retrieving part for extracting the inspected object region from the first memory; a design characteristic item data preparing part for preparing a first design characteristic item data by deriving a numerical value indicative of a design characteristic of the design data every first lattice region, the first lattice region being obtained by dividing the extracted inspected object region into lattices of the first size; a characteristic classification data preparing part for preparing a first characteristic classification data by classifying the first design characteristic item data into a desired number of groups; a third memory for storing therein a data on a sampling rate for extracting samples at random from the first characteristic classification data; a sampling part for extracting the first lattice regions at random from the first characteristic classification data at the sampling rate with respect to the number of the lattice regions belonging to the groups; a fourth memory for storing therein a defect inspection data concerning an actual defect and the degree of the defect which are obtained by inspecting places corresponding to the first lattice regions extracted at the sampling rate from a processed pattern which is processed on the basis of a design data; a design data processing part for acquiring second lattice regions by dividing the inspected object region into lattices of the second sizes so that a place causing the defect is arranged at the center thereof on the basis of the defect inspection data, for acquiring third lattice regions by dividing the inspected object region into lattices of the second size so that a non-defective place is arranged at the center thereof on the basis of the inspection result data, for deriving a numerical value indicative of a design characteristic of the design data every one of the second lattice regions to prepare a second design characteristic item data and for deriving a numerical value indicative of a design characteristic of the design data every one of the third lattice regions to prepare a third design characteristic item data every one of the third lattice regions; a fifth memory for storing therein a data on an observable process result relating to a processing of the pattern based on the design data; a process data processing part for collecting a value of a first process result corresponding to a pattern in the second lattice regions and a value of a second process result corresponding to a pattern in the third lattice regions, from the data on the process results respectively; and a defect occurrence rule preparing part for preparing a defect occurrence rule by correlating a combination of the second design characteristic item data and the value of the first process result with the defect and the degree of the defect and by correlating the a combination of the third design characteristic item data and the value of the second process result with the defect and the degree of the defect.
Preferably, in the semiconductor defect analyzing system according to the third aspect, the design data processing part changes the second size to prepare the second design characteristic item data and the third design characteristic item data with respect to the second lattice regions of a plurality of sizes and third lattice regions of a plurality of sizes respectively, the process data processing part collects the value of the first process result and the value of the second process result with respect to the second lattice region of the plurality of sizes and the third lattice region of the plurality of sizes respectively, and the defect occurrence rule preparing part prepares the defect occurrence rule by correlating each combination of each second size, the second design characteristic item data and the value of the first process result with the defect and the degree of the defect and by correlating each combination of each second size, the third design characteristic item data and the value of the second process result with the defect and the degree of the defect.
The defect inspection data may preferably be a data prepared on the comparison of an ideal shape data with a shape data of the defect in the processed pattern, the ideal shape data being a simulation result based on the design data.
The characteristic classification data preparing part may classify the design characteristic item data using a neural network.
In addition, the characteristic classification data preparing part may prepare the defect occurrence rule using a statistical technique including a decision tree.
According to a fourth aspect of the invention, there is provided a semiconductor design data modifying system comprising: a memory for storing therein a data on a defect occurrence rule obtained by analyzing a correlation between the presence of the defect and the degree of the defect and a combination of a design characteristic causing a defect and a value of a process result relating to the design characteristic; a pattern checking part for extracting a pattern capable of causing a defect from the design data on the basis of the defect occurrence rule; a design data modifying part for modifying the design data with respect to the extracted pattern to output a modified design data; a modified design data processing part for receiving a data on an optical lattice size and a data on an optional lattice interval as first parameters which are used to analyze the modified design data, for dividing the modified design data into optional combinations of the lattice interval and the lattice size, for deriving numerical values indicative of design characteristics of the modified design data with respect to the obtained lattice region, and for preparing a modified design characteristic item data; and an operation part for comparing the modified design characteristic item data with the defect occurrence rule and for calculating a defect probability which is a defect causing probability.
According to the fourth aspect of a semiconductor design data modifying system according to the present invention, the pattern checking part extracts the pattern capable of causing the defect from the design data on the basis of the defect occurrence rule, and the design modifying part modifies the design data with respect to the extracted pattern, so that it is possible to modify a design with some possibility of causing a defect in a design stage of a semiconductor device. In addition, the operation part compares the modified design characteristic item data with a defect occurrence rule to calculate a defect possibility, so that it is possible to previously estimate a defect occurring possibility due to the design in the design stage of the semiconductor device.
The defect occurrence rule may be supplied from the semiconductor defect analyzing system according to the second and third aspects.
It is preferable that a data on a desired threshold is applied to the operation part as a second parameter and that the semiconductor design data modifying system further comprises a re-modification command part for comparing the defect probability with the desired threshold and for supplying a command for modifying the modified design data again to the design data modifying part, the design data processing part and the operation part until the probability of the failure reaches the desired threshold or until the probability of the failure reaches a minimum value.
According to a fifth aspect of the present invention, there is provided a semiconductor design data modifying system comprising: a first memory for storing therein a design data of a semiconductor device; a data retrieving part for extracting an inspected object region from the first memory, the inspected object being a region serving as an object to be inspected; a design characteristic item data preparing part for deriving a numerical value indicative of a design characteristic of the design data every one of first lattice regions which are obtained by dividing the inspected object region extracted by the data retrieving part into lattices of a first size and for preparing a first design characteristic item data; a characteristic classification data preparing part for preparing a first characteristic classification data by classifying the first design characteristic item data into a desired number of groups; a sampling part for extracting the first lattice regions at random from the first characteristic classification data at a constant sampling rate with respect to the number of the first lattice regions belonging to the groups; a second memory for storing therein a defect inspection data on an actual defect and the degree of the defect which are obtained by inspecting a pattern of the first lattice regions of patterns processed on the basis of the design data, the first lattice regions being extracted at the sampling rate; a design data processing part for acquiring a second lattice region by dividing the inspected object region into lattices of an optional second size so that a place at which the defect occurs is arranged at the center thereof on the basis of the defect inspection data, and for acquiring a third lattice region by dividing the inspected object region into lattices of the second size so that a non-defective place of the processed pattern is arranged at the center thereof on the basis of the defect inspection data, for deriving a numerical value indicative of a design characteristic of the design data every one of the second lattice regions to prepare a second design characteristic item data and for deriving a numerical value indicative of a design characteristic of the design data every one of the third lattice regions to prepare a third design characteristic item data, the optional second size being given as a first parameter, and, the non-defective place being appropriately processed; a third memory for storing therein a data on an observable process result relating to a processing of the pattern based on the design data; a process data processing part for collecting a value of a first process result corresponding to a pattern in the second lattice region and a value of a second process result corresponding to a pattern in the third lattice region from the third memory respectively; a defect occurrence rule preparing part for preparing a defect occurrence rule by correlating a combination of the second design characteristic item data and the value of the first process result with the defect and the degree of the defect and by correlating a combination of the third design characteristic item data and the value of the second process result with the defect and the degree of the defect; a pattern checking part for extracting a pattern capable of causing a defect from the design data on the basis of the defect occurrence rule; a design data modifying part for modifying the design data with respect to the extracted pattern to output the modified design data; a modified design data processing part for obtaining a fourth lattice region by dividing the modified design data by an optional combination of an optional lattice interval and the lattices of an optional third size, and for deriving a numerical value indicative of a design characteristic of the design data with respect to the fourth lattice region to prepare a fourth design characteristic item data, the optional third size being given as a second parameter, and, the optional lattice interval being applied as a third parameter; and an operation part for comparing the fourth design characteristic item data with the defect occurrence rule to calculate a probability of a failure, which is a defect causing probability.
In the fifth aspect of the invention, it is advantageous that a desired threshold is given to the operation part as a fourth parameter and that semiconductor design data modifying system further comprises a re-modification command part for comparing the probability of the failure with the desired threshold and for supplying a command for modifying the modified design data again to the design data modifying part, the design data processing part and the operation part until the probability of the failure reaches the desired threshold or until the probability of the failure reaches the minimum value.
According to a sixth aspect of the present invention, there is provided a semiconductor inspecting method comprising the steps of: extracting an inspected object region from a design data of a semiconductor device and dividing the inspected object region by a lattice of an optional size to prepare lattice regions, the inspected object region serving as an object to be inspected; deriving a numerical value indicative of a design characteristic of the design data every one of the lattice regions to prepare a design characteristic item data; preparing a characteristic classification data by classifying the design characteristic item data into a desired number of groups; extracting the lattice regions at random from the characteristic classification data at a constant sampling rate with respect to the number of the lattice regions belonging to the group; actually inspecting a pattern of the lattice regions of a processed pattern which is processed on the basis of the design data, the pattern of the lattice regions having been extracted at the sampling rate, and acquiring a defect inspection data which is a data concerning a defect; and calculating the number of defects in the whole inspected object region on the basis of the defect inspection data, the characteristic classification data and the sampling rate.
According to the sixth aspect of the present invention, a semiconductor inspecting method comprises the steps of deriving a numerical value indicative of the design characteristic of the design data to prepare the design characteristic item data, classifying the design characteristic item data into the desired number of groups to prepare the characteristic classification data, and calculating the number of defects in the whole inspected object region on the basis of a defect inspection data, the characteristic classification data and a sampling rate, so that it is possible to more precisely quantify the defects due to the design of a semiconductor device.
In the sixth aspect, the step of acquiring the defect inspection data may preferably include a step of comparing the shape of a defect in the processed pattern with an ideal shape every one of the lattice regions which are extracted at the step of extracting the lattice regions, the ideal shape being the result of a simulation based on the design data, and preparing the defect inspection data on the basis of the result of the comparison.
Furthermore, the data concerning the defects may include a data on the degree of defects, and the step of calculating the number of defects may be a step of calculating the number of defects every degree of defects.
The step of preparing the characteristic classification data may be a step of classifying the design characteristic item data using a neural network.
In addition, the step of preparing the characteristic classification data may be a step of classifying the design characteristic item data using a statistical technique including a decision tree.
According to a seventh aspect of the present invention, there is provided a semiconductor defect analyzing method comprising the steps of: acquiring first lattice regions by dividing an inspected object region in the design data by a lattice having an optional size on the basis of a defect inspection data concerning an actual defect and a degree of the defect so that a place at which the defect occurs is arranged at the center thereof, deriving a numerical value indicative of a design characteristic of the design data every one of the first lattice regions and preparing a first design characteristic item data, the defect and the degree of the defect being obtained by inspecting a processed pattern which is processed on the basis of a design data; collecting a value of a first process result corresponding to a pattern in the first lattice regions on the basis of a data on an observable process result relating to a processing of the pattern based on the design data; acquiring second lattice regions by dividing the inspected object region by a lattice of the optional size on the basis of the defect inspection data so that an appropriate processed non-defective place is arranged at the center thereof, and deriving a numerical value indicative of a design characteristic of the design data every one of the second lattices and for preparing a second design characteristic item data; collecting a value of a second process result corresponding to a pattern in the second lattice regions from a data on the process result; and preparing a defect occurrence rule by correlating a combination of the first design characteristic item data and a value of the first process result with the defect and the degree of the defect and by correlating a combination of the second design characteristic item data and a value of the second process result with the defect and the degree of the defect.
According to a seventh aspect of the present invention, a semiconductor defect analyzing method comprises a step of preparing a defect occurrence rule by correlating a combination of the first design characteristic item data and the value of the first process result with the defect and the degree of the defect and by correlating a combination of the second design characteristic item data and the value of the second process result with the defect and the degree of the defect, so that it is possible to calculate a defect occurring probability with respect to the combination of a design characteristic causing the defect, the process result, the presence of the defect and the degree thereof.
In the seventh aspect, the defect inspection data is preferably a data prepared on the comparison of an ideal shape data with a shape data of the defect in the processed pattern, the ideal shape data being a simulation result based on the design data.
Furthermore, it is advantageous that the semiconductor defect analyzing method may further comprises a step of repeating sequentially the steps from the step of preparing the first design characteristic item data to the step of collecting the value of the second process result while changing the size of the lattices to prepare the first design characteristic item data and the value of the first process result with respect to each of the first lattice regions of a plurality of sizes and to prepare the second design characteristic item data and the value of the second process result with respect to each of the second lattice regions of the plurality of sizes before the step of acquiring the correlation and the step of preparing the defect occurrence rule.
According to an eighth aspect of the present invention, there is provided a semiconductor defect analyzing method comprising the steps of: extracting an inspected object region from a design data of a semiconductor device and preparing first lattice regions by dividing the inspected object region into lattices of an optional first size, the inspected object region serving as an object to be inspected, and, the optional first size being given as a first parameter; preparing a first design characteristic item data by deriving a numerical number indicative of a design characteristic of the design data every one of the first lattice regions; preparing a characteristic classification data by classifying the design characteristic item data into a desired number of groups; extracting the lattice regions at random from the characteristic classification data at a constant sampling rate with respect to the number of the lattice regions belonging to the groups; acquiring second lattice regions by dividing the inspected object region in the design data into lattices of a second size so that a place causing the defect is arranged at the center thereof on the basis of a defect inspection data relating to an actual defect and a degree of the defect of the processed patterns which are processed on the basis of the design data, the second size being given as a second parameter, and, the actual defect and the degree of the defect being obtained by inspecting a pattern of the lattice region which is extracted at the sampling rate; deriving a numerical value indicative of a design characteristic of the design data every one of the second lattice regions to prepare a second design characteristic item data; collecting a value of a first process result corresponding to a pattern in the second lattice regions on the basis of a data on an observable process result relating to a processing of the pattern based on the design data; obtaining third lattice regions by dividing the inspected object region into lattices of the second size so that a processed non-defective place is arranged at the center thereof on the basis of the defect inspection data and deriving a numerical value indicative of a design characteristic of the design data every one of the obtained third lattice regions to prepare a third design characteristic item data; collecting a value of a second process result corresponding to a pattern in the third lattice regions from a data on the process result; preparing a defect occurrence rule by acquiring a first correlation between the defect and the degree of the defect and a combination of the second design characteristic item data and the value of the first process result, and a second correlation between the value of the second process result and the defect and the degree of the defect and a combination of the third design characteristic item data.
In the eighth aspect, it is advantageous that the semiconductor defect analyzing method may further comprises a step of repeating sequentially the steps from the step of preparing the second design characteristic item data to the step of collecting the value of the second process result while changing the second size of the lattices to prepare the second design characteristic item data and the value of the first process result with respect to each of the second lattice regions of a plurality of sizes and to prepare the third design characteristic item data and the value of the second process result with respect to each of the third lattice regions of the plurality of sizes before the step of acquiring the first correlation and the second correlation and the step of preparing the defect occurrence rule.
The step of preparing the defect occurrence rule may acquire the correlations using a neural network or a statistical technique including a decision tree.
In the seventh aspect, the defect inspection data is preferably a data prepared on the comparison of an ideal shape data with a shape data of the defect in the processed pattern, the ideal shape data being a simulation result based on the design data.
According to a ninth aspect of the present invention, there is provided a semiconductor design data modifying method comprising the steps of: extracting a pattern capable of causing a defect from a design data of a semiconductor device on the basis of a defect occurrence rule which is prepared on the basis of the design data and which is indicative of a correlation of the presence of the defect and the degree of the defect and a combination of a design characteristic of the design data causing a defect and a value of a process result relating to the design characteristic; modifying the design data with respect to the extracted pattern to output a modified design data; acquiring lattice regions by dividing the modified design data by an optional combination of a lattice of an optional size and an optional lattice interval, deriving a numerical value indicative of a design characteristic of the modified design data with respect to each of the lattice regions and preparing a modified design characteristic item data; and comparing the modified design characteristic item data with the defect occurrence rule to calculate a probability of a failure, which is a defect causing probability.
According to the ninth aspect of the present invention, the semiconductor design data modifying method comprises the steps of extracting a pattern capable of causing the defect from the design data on the basis of the defect occurrence rule, and modifying the design data with respect to the extracted pattern, so that it is possible to modify a design with some possibility of causing the defect in the design stage of a semiconductor device. The semiconductor design data modifying method further comprises the step of comparing the modified design characteristic item data with the defect occurrence rule to calculate a probability of a failure, so that it is possible to previously estimate a possibility of generating the failure due to the design of a semiconductor device in a design stage of a semiconductor device.
In the ninth aspect, the defect occurrence rule is preferably prepared by the semiconductor defect analyzing method according to the sixth or seventh aspect.
According to a tenth aspect of the present invention, there is provided a semiconductor design data modifying method comprising the steps of: extracting an inspected object region from a design data of a semiconductor device and preparing first lattice regions by dividing the inspected object region into lattices of an optional first size, the inspected object region serving as an object to be inspected, and, the optional first size being given as a first parameter; preparing a first design characteristic item data by deriving a numerical value indicative of a design characteristic of the design data every one of the first lattice regions; preparing a first characteristic classification data by classifying the design characteristic item data into a desired number of groups; extracting the first lattice regions at random from the first characteristic classification data at a constant sampling rate with respect to the number of the lattice regions belonging to the groups; obtaining a defect inspection data concerning an actual defect and a degree of the defect by inspecting a pattern of the first lattice regions, the actual defect and the degree of the defect being extracted at the sampling rate; acquiring second lattice regions by dividing the inspected object region in the design data into lattices of a second size on the basis of the defect inspection data concerning the actual defect and the degree of the defect of processed patterns so that a place causing the defect is arranged at the center thereof on the basis of the design data and preparing a second design characteristic item data by deriving a numerical value indicative of a design characteristic of the design data every one of the second lattice regions, the second size being given as a second parameter; collecting a value of a first process result corresponding to a pattern in the second lattice regions on the basis of a data on an observable process result relating to a processing of the pattern based on the design data; acquiring third lattice regions by dividing the inspected object region into lattices of the second size on the basis of the defect inspection data so that a non-defective place processed on the basis of the defect inspection data is arranged at the center thereof and preparing a third design characteristic item data by deriving a numerical value indicative of a design characteristic of the design data every one of the third lattice regions; collecting a value of a second process result corresponding to a pattern in the third lattice regions from a data on the observable process result; preparing a defect occurrence rule by acquiring a first correlation between the defect and the degree of the defect and a combination of the second design characteristic item data and the value of the first process result and by acquiring a second correlation between the defect and the degree of the defect and a combination of the third design characteristic item data and the value of the second process result; extracting a pattern capable of causing the defect from the design data on the basis of the defect occurrence rule; modifying the design data with respect to the extracted pattern to output the modified design data; obtaining fourth lattice regions by dividing the modified design data by an optional combination of the lattice of the third size and an optional lattice interval, the optional third size being given as a third parameter, and, the optional lattice interval being given as a fourth parameter; preparing a fourth design characteristic item data by deriving a numerical value indicative of a design characteristic of the modified design data with respect to each of the fourth lattice regions; and calculate a probability of a failure, which is a defect causing probability, by comparing the fourth design characteristic item data with the defect occurrence rule.
The semiconductor design data modifying method according to the tenth aspect preferably further comprises a step of repeating the steps from the step of extracting the pattern capable of causing the defect to the step of calculating the defect probability while comparing the defect probability with a desired threshold until the probability of the failure reaches the desired threshold or until the probability of the failure reaches the minimum value.
According to a eleventh aspect of the present invention, there is provided a computer readable recorded medium in which a program for causing a computer to execute a semiconductor inspecting method has been recorded, the semiconductor inspecting method comprising the steps of: extracting an inspected object region from a design data of a semiconductor device and dividing the inspected object region by a lattice of an optional size to prepare lattice regions, the inspected object region serving as an object to be inspected; deriving a numerical value indicative of a design characteristic of the design data every one of the lattice regions to prepare a design characteristic item data; preparing a characteristic classification data by classifying the design characteristic item data into a desired number of groups; extracting the lattice regions at random from the characteristic classification data at a constant sampling rate with respect to the number of the lattice regions belonging to the group; actually inspecting a pattern of the lattice regions of a processed pattern which is processed on the basis of the design data, the pattern of the lattice regions having been extracted at the sampling rate, and acquiring a defect inspection data which is a data concerning a defect; and calculating the number of defects in the whole inspected object region on the basis of the defect inspection data, the characteristic classification data and the sampling rate.
In the eleventh aspect, the step of calculating the number of defects may preferably include a step of comparing the shape of a defect in the processed pattern with an ideal shape every one of the lattice regions which are extracted at the step of extracting the lattice regions, the ideal shape being the result of a simulation based on the design data, and preparing the defect inspection data on the basis of the result of the comparison.
Furthermore, the data concerning the defects may include a data on the degree of defects, and the step of calculating the number of defects may be a step of calculating the number of defects every degree of defects.
The step of preparing the characteristic classification data may be a step of classifying the design characteristic item data using a neural network.
According to a twelfth aspect of the present invention, there is provided a computer readable recorded medium in which a program for causing a computer to execute a semiconductor defect analyzing method, the semiconductor defect analyzing method comprising the steps of: acquiring first lattice regions by dividing an inspected object region in the design data by a lattice having an optional size on the basis of a defect inspection data concerning an actual defect and a degree of the defect so that a place at which the defect occurs is arranged at the center thereof, deriving a numerical value indicative of a design characteristic of the design data every one of the first lattice regions and preparing a first design characteristic item data, the defect and the degree of the defect being obtained by inspecting a processed pattern which is processed on the basis of a design data; collecting a value of a first process result corresponding to a pattern in the first lattice regions on the basis of a data on an observable process result relating to a processing of the pattern based on the design data; acquiring second lattice regions by dividing the inspected object region by a lattice of the optional size on the basis of the defect inspection data so that an appropriate processed non-defective place is arranged at the center thereof, and deriving a numerical value indicative of a design characteristic of the design data every one of the second lattices and for preparing a second design characteristic item data; collecting a value of a second process result corresponding to a pattern in the second lattice regions from a data on the process result; and preparing a defect occurrence rule by correlating a combination of the first design characteristic item data and a value of the first process result with the defect and the degree of the defect and by correlating a combination of the second design characteristic item data and a value of the second process result with the defect and the degree of the defect.
In the twelfth aspect, it is advantageous that the semiconductor defect analyzing method may further comprises a step of repeating sequentially the steps from the step of preparing the first design characteristic item data to the step of collecting the value of the second process result while changing the size of the lattices to prepare the first design characteristic item data and the value of the first process result with respect to each of the first lattice regions of a plurality of sizes and to prepare the second design characteristic item data and the value of the second process result with respect to each of the second lattice regions of the plurality of sizes before the step of acquiring the correlation and the step of preparing the defect occurrence rule.
According to a thirteenth aspect of the present invention, there is provided a computer readable recorded medium in which a program for causing a computer to execute a semiconductor defect analyzing method, the semiconductor defect analyzing method comprising the steps of: extracting an inspected object region from a design data of a semiconductor device and preparing first lattice regions by dividing the inspected object region into lattices of an optional first size, the inspected object region serving as an object to be inspected, and, the optional first size being given as a first parameter; preparing a first design characteristic item data by deriving a numerical number indicative of a design characteristic of the design data every one of the first lattice regions; preparing a characteristic classification data by classifying the design characteristic item data into a desired number of groups; extracting the lattice regions at random from the characteristic classification data at a constant sampling rate with respect to the number of the lattice regions belonging to the groups; acquiring second lattice regions by dividing the inspected object region in the design data into lattices of a second size so that a place causing the defect is arranged at the center thereof on the basis of a defect inspection data relating to an actual defect and a degree of the defect of the processed patterns which are processed on the basis of the design data, the second size being given as a second parameter, and, the actual defect and the degree of the defect being obtained by inspecting a pattern of the lattice region which is extracted at the sampling rate; deriving a numerical value indicative of a design characteristic of the design data every one of the second lattice regions to prepare a second design characteristic item data; collecting a value of a first process result corresponding to a pattern in the second lattice regions on the basis of a data on an observable process result relating to a processing of the pattern based on the design data; obtaining third lattice regions by dividing the inspected object region into lattices of the second size so that a processed non-defective place is arranged at the center thereof on the basis of the defect inspection data and deriving a numerical value indicative of a design characteristic of the design data every one of the obtained third lattice regions to prepare a third design characteristic item data; collecting a value of a second process result corresponding to a pattern in the third lattice regions from a data on the process result; preparing a defect occurrence rule by acquiring a first correlation between the defect and the degree of the defect and a combination of the second design characteristic item data and the value of the first process result, and a second correlation between the value of the second process result and the defect and the degree of the defect and a combination of the third design characteristic item data.
In the thirteenth aspect, it is advantageous that the semiconductor defect analyzing method may further comprises a step of repeating sequentially the steps from the step of preparing the second design characteristic item data to the step of collecting the value of the second process result while changing the second side of the lattices to prepare the second design characteristic item data and the value of the first process result with respect to each of the second lattice regions of a plurality of sizes and to prepare the third design characteristic item data and the value of the second process result with respect to each of the third lattice regions of the plurality of sizes before the step of acquiring the first correlation and the second correlation and the step of preparing the defect occurrence rule.
The step of preparing the defect occurrence rule may acquire the correlations using a neural network or a statistical technique including a decision tree.
In the thirteenth aspect, the defect inspection data is preferably a data prepared on the comparison of an ideal shape data with a shape data of the defect in the processed pattern, the ideal shape data being a simulation result based on the design data.
According to a fourteenth aspect of the present invention, there is provided a computer readable recorded medium in which a program for causing a computer to execute a semiconductor design data modifying method, the semiconductor design data modifying method comprising the steps of: extracting a pattern capable of causing a defect from a design data of a semiconductor device on the basis of a defect occurrence rule which is prepared on the basis of the design data and which is indicative of a correlation of the presence of the defect and the degree of the defect and a combination of a design characteristic of the design data causing a defect and a value of a process result relating to the design characteristic; modifying the design data with respect to the extracted pattern to output a modified design data; acquiring lattice regions by dividing the modified design data by an optional combination of a lattice of an optional size and an optional lattice interval, deriving a numerical value indicative of a design characteristic of the modified design data with respect to each of the lattice regions and preparing a modified design characteristic item data; and comparing the modified design characteristic item data with the defect occurrence rule to calculate a probability of a failure, which is a defect causing probability.
In the fourteenth aspect, the defect occurrence rule is preferably prepared by the semiconductor defect analyzing method according to the sixth or seventh aspect.
According to a fifteenth aspect of the present invention, there is provided a computer readable recorded medium in which a program for causing a computer to execute a semiconductor design data modifying method, the semiconductor design data modifying method comprising the steps of: extracting an inspected object region from a design data of a semiconductor device and preparing first lattice regions by dividing the inspected object region into lattices of an optional first size, the inspected object region serving as an object to be inspected, and, the optional first size being given as a first parameter; preparing a first design characteristic item data by deriving a numerical value indicative of a design characteristic of the design data every one of the first lattice regions; preparing a first characteristic classification data by classifying the design characteristic item data into a desired number of groups; extracting the first lattice regions at random from the first characteristic classification data at a constant sampling rate with respect to the number of the lattice regions belonging to the groups; obtaining a defect inspection data concerning an actual defect and a degree of the defect by inspecting a pattern of the first lattice regions, the actual defect and the degree of the defect being extracted at the sampling rate; acquiring second lattice regions by dividing the inspected object region in the design data into lattices of a second size on the basis of the defect inspection data concerning the actual defect and the degree of the defect of processed patterns so that a place causing the defect is arranged at the center thereof on the basis of the design data and preparing a second design characteristic item data by deriving a numerical value indicative of a design characteristic of the design data every one of the second lattice regions, the second size being given as a second parameter; collecting a value of a first process result corresponding to a pattern in the second lattice regions on the basis of a data on an observable process result relating to a processing of the pattern based on the design data; acquiring third lattice regions by dividing the inspected object region into lattices of the second size on the basis of the defect inspection data so that a non-defective place processed on the basis of the defect inspection data is arranged at the center thereof and preparing a third design characteristic item data by derive a numerical value indicative of a design characteristic of the design data every one of the third lattice regions; collecting a value of a second process result corresponding to a pattern in the third lattice regions from a data on the observable process result; preparing a defect occurrence rule by acquiring a first correlation between the defect and the degree of the defect and a combination of the second design characteristic item data and the value of the first process result and by acquiring a second correlation between the defect and the degree of the defect and a combination of the third design characteristic item data and the value of the second process result; extracting a pattern capable of causing the defect from the design data on the basis of the defect occurrence rule; modifying the design data with respect to the extracted pattern to output the modified design data; obtaining fourth lattice regions by dividing the modified design data by an optional combination of the lattice of the third size and an optional lattice interval, the optional third size being given as a third parameter, and, the optional lattice interval being given as a fourth parameter; preparing a fourth design characteristic item data by deriving a numerical value indicative of a design characteristic of the modified design data with respect to each of the fourth lattice regions; and calculate a probability of a failure, which is a defect causing probability, by comparing the fourth design characteristic item data with the defect occurrence rule.
The recorded medium according to the fifteenth aspect preferably further comprises a step of repeating the steps from the step of extracting the pattern capable of causing the defect to the step of calculating the probability of the failure while comparing the probability of the failure with a desired threshold until the probability of the failure reaches the desired threshold or until the probability of the failure reaches the minimum value.
In the above described aspects, the comparison of a data on a defect shape of a processed pattern with an ideal shape is preferably carried out using an image acquired by an electron microscope or an image acquired by an optical technique.